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Dataset: Rad-Hard and ULP FPGA with "Full" Functionality, Phase II
Provided by National Aeronautics and Space Administration
Updated 12 Nov 2020

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Dataset summary

The dataset on this page is a cache of the dataset It is a snapshot of the dataset as it appeared on 06 Jun 2021 22:39 GMT. The current dataset could have changed in the meantime. Attribution: Contains data retrieved from

RNET has demonstrated the feasibility of developing an innovative radiation hardened (RH) and ultra low power (ULP) field programmable gate array (FPGA), called the RH/ULP FPGA. The design utilizes an advanced SOI process technology. It is the vision of RNET to develop a family of radiation hardened FPGA products with a variety of features including programmable logic, configurable analog functions, soft/hardcore microprocessor, dedicated DSP functions, I/O, dedicated memory blocks, memory controllers, global clock, and JTAG interface. In addition, specialized circuits for mitigation of TID/temperature effects, radiation hardened by design SEU techniques, and memory scrubbing are planned. Our vision at the conclusion of this proposed SBIR is to fabricate a "commercial" RH/ULP FPGA with the most important features listed. Ideally the FPGA to be developed under the proposed Phase 2 would contain all of these features, but due to the limitation of funds and allotted time, a scaled down ve...

Dataset:Rad-Hard and ULP FPGA with "Full" Functionality, Phase II
Provider:National Aeronautics and Space Administration
Licence:License information is derived automatically. Refer to source for license information before using this data.
License not specified
Country:United States of America

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